相关参考文献
注意:仅列出部分参考文献,下载原文获取全部文献信息。DTCO Launches Moore's Law Over the Feature Scaling Wall
V Moroz et al.
2020 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) (2020)
Simulation and comparative study on analog/RF and linearity performance of III-V semiconductor-based staggered heterojunction and InAs nanowire(nw) Tunnel FET
Sudhansu Mohan Biswal et al.
MICROSYSTEM TECHNOLOGIES-MICRO-AND NANOSYSTEMS-INFORMATION STORAGE AND PROCESSING SYSTEMS (2019)
Stress-Induced Variability Studies in Tri-Gate FinFETs with Source/Drain Stressor at 7nm Technology Nodes
T. P. Dash et al.
JOURNAL OF ELECTRONIC MATERIALS (2019)
Analytical computation of electrical parameters in GAAQWT and CNTFET with identical configuration using NEGF method
Arpan Deyasi et al.
INTERNATIONAL JOURNAL OF ELECTRONICS (2018)
Back to the Future: Digital Circuit Design in the FinFET Era
Xinfei Guo et al.
JOURNAL OF LOW POWER ELECTRONICS (2017)
An analytical model of triple-material double-gate metal-oxide-semiconductor field-effect transistor to suppress short-channel effects
Biswajit Baral et al.
INTERNATIONAL JOURNAL OF NUMERICAL MODELLING-ELECTRONIC NETWORKS DEVICES AND FIELDS (2016)
Impact of Fin Width Scaling on RF/Analog Performance of Junctionless Accumulation-Mode Bulk FinFET
Kalyan Biswas et al.
ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS (2016)
Impact of Sidewall Passivation and Channel Composition on InxGa1-xAs FinFET Performance
Arun V. Thathachary et al.
IEEE ELECTRON DEVICE LETTERS (2015)
Effect of gate engineering in JLSRG MOSFET to suppress SCEs: An analytical study
Surajit Bari et al.
PHYSICA E-LOW-DIMENSIONAL SYSTEMS & NANOSTRUCTURES (2015)
Analytical subthreshold modeling of dual material gate engineered nano-scale junctionless surrounding gate MOSFET considering ECPE
Sudhansu Mohan Biswal et al.
SUPERLATTICES AND MICROSTRUCTURES (2015)
Implementation of the Density Gradient Quantum Corrections for 3-D Simulations of Multigate Nanoscaled Transistors
Antonio J. Garcia-Loureiro et al.
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS (2011)
Strain optimization in ultrathin body transistors with silicon-germanium source and drain stressors
Anuj Madan et al.
JOURNAL OF APPLIED PHYSICS (2008)
Low-field electron mobility model for ultrathin-body SOI and double-gate MOSFETs with extremely small silicon thicknesses
Susanna Reggiani et al.
IEEE TRANSACTIONS ON ELECTRON DEVICES (2007)
Extraction of the top and sidewall mobility in FinFETs and the impact of fin-patterning processes and gate dielectrics on-mobility
Vikram V. Iyengar et al.
IEEE TRANSACTIONS ON ELECTRON DEVICES (2007)
Device structures and carrier transport properties of advanced CMOS using high mobility channels
S. Takagi et al.
SOLID-STATE ELECTRONICS (2007)
Hybrid-orientation technology (HOT): Opportunities and challenges
M Yang et al.
IEEE TRANSACTIONS ON ELECTRON DEVICES (2006)