Vertically stacked, low-voltage organic ternary logic circuits including nonvolatile floating-gate memory transistors

Multi-valued logic (MVL) circuits based on heterojunction transistor (HTR) have emerged as an effective strategy for high-density information processing without increasing the circuit complexity. Herein, an organic ternary logic inverter (T-inverter) is demonstrated, where a nonvolatile floating-gate flash memory is employed to control the channel conductance systematically, thus realizing the stabilized T-inverter operation. The 3-dimensional (3D) T-inverter is fabricated in a vertically stacked form based on all-dry processes, which enables the high-density integration with high device uniformity. In the flash memory, ultrathin polymer dielectrics are utilized to reduce the programming/erasing voltage as well as operating voltage. With the optimum programming state, the 3D T-inverter fulfills all the important requirements such as full-swing operation, optimum intermediate logic value (similar to V-DD/2), high DC gain exceeding 20 V/V as well as low-voltage operation (< 5 V). The organic flash memory exhibits long retention characteristics (current change less than 10% after 10(4)s), leading to the long-term stability of the 3D T-inverter. We believe the 3D T-inverter employing flash memory developed in this study can provide a useful insight to achieve high-performance MVL circuits.

Automated summary

Researchers have developed a multi-valued logic circuit based on heterojunction transistors, which utilizes nonvolatile floating-gate flash memory to control channel conductance and achieve stable operation of ternary logic inverters. The 3D inverters, fabricated in a vertically stacked form, demonstrate high-density integration and device uniformity. The organic flash memory exhibits long retention characteristics, ensuring long-term stability of the 3D inverters. This study provides valuable insights for achieving high-performance multi-valued logic circuits.