Low Power CMOS Design of Phase Locked Loop for Fastest Frequency Acquisition at Various Nanometer Technologies

The performance of any VLSI circuit depends on its design architecture. Designing a power-efficient device is the most challenging criteria. In most telecommunication applications, Phase Lock Loop (PLL) plays a major role. It creates an response signal with the same phase as the input signal. The main problem in PLL design is to achieve a high operating frequency while using the least amount of power. The complete power dissipation of PLL can be condensed by minimising the power consumption of the Phase Frequency Detector, which is a significant block of PLL. All the results related to the proposed designs have been obtained using Tanner Tool 45, 180, and 250 nm CMOS processes. The proposed PLL design shows a reduction in power of up to 180.85 microwatts, which is significantly 3% lower than the existing PLL. The time delay obtained in the proposed PLL design is 6.872 ns, which is 10% less than the existing PLL design, and the obtained PDP is 12% less than the existing PLL design. The suggested design also has a greater flow frequency of 2.31 GHz, making it a viable circuit for high-performance PLL systems, according to simulation data.

Automated summary

The performance of VLSI circuits depends on their design architecture, and designing a power-efficient device is the main challenge. The Phase Lock Loop (PLL) plays a significant role in telecommunications applications, and achieving a high operating frequency with minimal power consumption is the main concern. This study proposes a PLL design that reduces power consumption by minimizing the Phase Frequency Detector's power consumption, resulting in a 3% decrease compared to existing designs. Additionally, the proposed design has lower time delay and PDP, making it a viable circuit for high-performance PLL systems.