相关参考文献
注意：仅列出部分参考文献，下载原文获取全部文献信息。A Square Wave-Based Digital Foreground Calibration Algorithm of a Pipeline ADC Using Approximate Harmonic Sampling
Shatadal Chatterjee et al.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS (2021)
Background Calibration of Bit Weights in Pipelined-SAR ADCs Using Paired Comparators
Jie Sun et al.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS (2020)
A 14-bit 200-Ms/s SHA-Less Pipelined ADC With Aperture Error Reduction
Peilin Yang et al.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS (2020)
Analysis and Design of a Large Dither Injection Circuit for Improving Linearity in Pipelined ADCs
Congyi Zhu et al.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS (2019)
A 12-Bit Time-Interleaved 400-MS/s Pipelined ADC With Split-ADC Digital Background Calibration in 4,000 Conversions/Channel
Tsung-Chih Hung et al.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS (2019)
A Low-Power Low-Cost On-Chip Digital Background Calibration for Pipelined ADCs
Xizhu Peng et al.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS (2019)
A Single Channel Split ADC Structure for Digital Background Calibration in Pipelined ADCs
Mohammad Ali Montazerolghaem et al.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS (2017)
Foreground calibration technique of a pipeline ADC using capacitor ratio of Multiplying Digital-to-Analog Converter (MDAC)
Sounak Roy et al.
MICROELECTRONICS JOURNAL (2013)
A 10-Bit 500-MS/s 55-mW CMOS ADC
Ashutosh Verma et al.
IEEE JOURNAL OF SOLID-STATE CIRCUITS (2009)
A 12-Bit 200-MHz CMOS ADC
Bibhu Datta Sahoo et al.
IEEE JOURNAL OF SOLID-STATE CIRCUITS (2009)
Background interstage gain calibration technique for pipelined ADCs
JP Keane et al.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS (2005)
Design techniques for a pipelined ADC without using a front-end sample-and-hold amplifier
DY Chang
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS (2004)
Radix-based digital calibration techniques for multi-stage recycling pipelined ADCs
DY Chang et al.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS (2004)
Background calibration techniques for multistage pipelined ADCs with digital redundancy
JP Li et al.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING (2003)
分享论文
