期刊
IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS
卷 18, 期 5, 页码 2934-2942出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TII.2021.3104285
关键词
Task analysis; Field programmable gate arrays; Kernel; Delays; Switches; Synchronization; Program processors; Control design; field programmable gate arrays; high-level synthesis (HLS); multicore processing; power conversion; real-time (RT) systems; runtime; software (SW) architecture
This article introduces a codesign workflow and a runtime architecture for digitally controlled switch-mode power conversion systems. By using a combination of multicore application processors and FPGAs in a general-purpose SoC, along with high-level synthesis, multirate control algorithms can be deployed and executed in real-time.
Digitally controlled switch-mode power conversion systems require an embedded computing platform to execute, in real-time (RT), closed-loop algorithms that regulate the power flow. Since legacy control software design is traditionally rooted to single-core processors, recent trends in power electronics toward faster switching devices and multilevel topologies will challenge their computational capacity and reliability to meet RT deadlines. With Internet-of-Things driving down the cost of a general-purpose system-on-chip (SoC), combining a multicore application processor and a field-gate programmable array (FPGA) on single device, this article introduces a codesign workflow and a runtime architecture for the heterogeneous deployment of multirate control algorithms. Code migration toward the FPGA exploits high-level synthesis, while a Linux-Xenomai dual-kernel operating system manages the synchronization and the parallel execution of the tasks. Following sections will describe and benchmark the selected key technologies and validate them on a small-scale grid-connected converter emulator.
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