期刊
IEEE TRANSACTIONS ON ELECTRON DEVICES
卷 69, 期 5, 页码 2543-2551出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2022.3158627
关键词
Logic gates; JFETs; Silicon carbide; Breakdown voltage; Leakage currents; Electric breakdown; Voltage measurement; JFET; output characteristics; sidewall implantation; silicon carbide (SiC); super junction (SJ); third-quadrant
资金
- National Natural Science Foundation of China [52107213]
- China Postdoctoral Science Foundation [2021M692765]
This article presents a characterization of SiC super junction JFETs fabricated by sidewall implantation with different mesa widths and termination designs. The study focuses on the breakdown voltage, on-resistance, and performance in different operating modes. The research provides insights into optimizing the device design and improving its performance in various applications.
Silicon carbide (SiC) super junction (SJ) JFETs fabricated by sidewall implantation with different mesa-widths (MWs) and termination designs are characterized in this article. The device with an MW of 1.8 mu m and active area of 0.104 mm(2) achieves a breakdown voltage of 1086 V and a specific on-resistance of 0.98 m omega,center dot,cm(2). The first-quadrant output and transfer characteristics are presented, from which the on-resistance and pinch-off voltage are extracted and analyzed. The pinch-off voltage shows great stability against the variation of temperature. The forward blocking characteristics under different gate voltages and with different terminations are presented. The gate needs to be negatively biased below the hold-off voltage to prevent the premature breakdown caused by drain-induced barrier-lowering (DIBL) effect. The termination with narrow mesas in the x-direction and trapezoidal mesas in the y-direction is found to have the highest breakdown voltage, due to its optimized net charge distribution. The third-quadrant output characteristics are presented. Under forward-off gate voltage, the third-quadrant turn-on voltage is found to be determined by the difference of hold-off and pinch-off voltages, and there is a tradeoff between the absolute third-quadrant voltage drop ( $| V_{on}|$ ) and the maximum current before gate junction turn-on ( $J_{umax}$ ). The third-quadrant performance can be improved by using forward-on gate voltage, a $| V_{on}|$ lower than 0.2 V (at 100 A/cm(2)) and a $J_{umax}$ larger than 500 A/cm(2) are achieved. Finally, the whole output characteristics are modeled to facilitate the device design in different applications.
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