A 625kHz-BW, 79.3dB-SNDR Second-Order Noise-Shaping SAR ADC Using High-Efficiency Error-Feedback Structure

This brief presents a compact and energy efficient noise-shaping successive-approximation-register (NS-SAR) analog-to-digital converter (ADC) based on the error-feedback (EF) structure. Different from most prior works adopting the cascaded integrator feed-forward (CIFF) structure, the proposed architecture employs unity-gain buffer and delay elements operated in a ping-pong manner to perform EF function. Since to the lossless residue extraction and summation, it exhibits high efficiency in realizing the strong noise-shaping (NS) effect. Fabricated in a 65-nm 1P9M CMOS technology, the prototype NS-SAR ADC consumes 113.02 mu W when operating at a 1.2-V supply voltage and at a sampling rate of 20 MS/s. It achieves a peak Schreier FoM of 176.73 dB with a signal to noise and distortion-ratio (SNDR) of 79.3 dB at an oversampling ratio (OSR) of 16.

Automated summary

This brief introduces a compact and energy efficient noise-shaping successive-approximation-register (NS-SAR) analog-to-digital converter (ADC) based on the error-feedback (EF) structure. The proposed architecture utilizes unity-gain buffer and delay elements operated in a ping-pong manner to perform EF function, resulting in high efficiency in achieving strong noise-shaping (NS) effect. The prototype NS-SAR ADC achieves impressive performance with low power consumption.