期刊
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
卷 69, 期 3, 页码 1044-1048出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCSII.2021.3125407
关键词
Direction-of-arrival estimation; Estimation; Hardware; Antenna arrays; Antennas; Array signal processing; Radio frequency; Hybrid antenna array; unequal-sized subarrays; direction-of-arrival (DoA); beamspace processing; application-specific integrated circuit (ASIC)
资金
- National Natural Science Foundation of China [62001121, 61525401]
- China Postdoctoral Science Foundation [2020M670994]
- Innovation Program of Shanghai Municipal Education Commission [201701-07-00-07-E00026]
This article introduces an efficient hardware beamspace DoA estimator for unequal-sized subarrays. By optimizing the algorithm and hardware design, the number of multiplication operations is reduced by 75% without significant performance loss. Experimental results show that the proposed hardware architecture achieves a small core area and high clock frequency in 28-nm technology.
Hybrid antenna array consisting of analog subarrays has been widely used for beamforming in millimeter-wave communication systems. Due to the hybrid structure, direction-of-arrival (DoA) estimation, which is essential to beam adjustment, has to be performed at the beamspace. In our previous work, unequal-sized subarrays has been proposed for beamspace DoA estimation because it can resolve the ambiguity problem, i.e., the DoA estimate at the beamspace may be non-unique. In this brief, we develop and implement a hardware-efficient beamspace DoA estimator dedicated for unequal-sized subarrays. Specifically, the proposed algorithm is tailored for hardware implementation such that the number of multiplications is reduced by 75% without significant performance loss. The proposed hardware architecture is layouted in 28-nm technology with a core area of 0.09 mm(2), a hardware complexity of 132 kilogate equivalents (kGE), and a clock frequency of 2.17 GHz.
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