期刊
IEEE JOURNAL OF SOLID-STATE CIRCUITS
卷 57, 期 6, 页码 1594-1609出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2021.3124971
关键词
Oscillators; Transistors; Harmonic analysis; Voltage; Zero voltage switching; Transformers; Q-factor; Differential and common-mode resonances; even-harmonic class-E; figure of merit (FoM); harmonic shaping; impulse sensitivity function (ISF); poly-ground-shielded transformer
This article presents a high-performance even-harmonic class-E CMOS oscillator with excellent phase noise performance, achieved through a customized resonant circuit and ZVS/ZDS conditions to improve power efficiency and reduce noise-to-phase noise conversion. The implemented oscillator performs well at high frequencies and exhibits improved characteristics compared to existing CMOS oscillators.
This article proposes the theory and implementation of an even-harmonic class-E CMOS oscillator that displays an excellent phase noise performance. Starting from zero voltage switching (ZVS) and zero derivative switching (ZDS) conditions, expressions for drain voltage and current waveforms are derived. Based on a 1:1 transformer, a custom-designed tank is proposed, which satisfies ZVS and ZDS conditions for the core transistors, provides high-Q resonances at both fundamental and second harmonics of the oscillation frequency, and yields a passive voltage gain from the drain to the gate of the core transistors. Satisfying ZVS and ZDS conditions reduces the overlap between the voltage and current waveforms of the transistor that increases the power efficiency of the oscillator. Furthermore, it widens the flat span of the semi half-sinusoidal voltage waveform, where the impulse sensitivity function (ISF) is negligible. Therefore, the conversion of the core transistor noise to phase noise is reduced. These features improve the oscillator's figure of merit (FoM) in comparison with state-of-the-art CMOS oscillators. The prototype of the even-harmonic class-E oscillator is implemented in a 0.18-mu m CMOS technology. At 4 GHz, it exhibits a phase noise of -152.75 dBc/Hz at a 10-MHz offset while providing a 10.6% tuning range. The corresponding FoM is 197.9 dBc/Hz. The circuit draws 7 mA from a 0.7-V supply, and the die area is 0.23 mm(2).
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