4.6 Article

Linking Room- and Low-Temperature Electrical Performance of MOS Gate Stacks for Cryogenic Applications

期刊

IEEE ELECTRON DEVICE LETTERS
卷 43, 期 5, 页码 674-677

出版社

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2022.3162368

关键词

Logic gates; Cryogenics; MOSFET; Tin; Hall effect; Silicon; Qubit; High performance computing; quantum computing; cryogenic MOSFET; hall measurement

资金

  1. imec through the Quantum Computing imec Industrial Affiliation Program (IIAP)
  2. European Union [951852]
  3. Ministry of Science and Technology, Taiwan [MOST 111-2636-E-006-023, 110-2218-E-006030-MBK]

向作者/读者索取更多资源

This study investigates the quality of four different gate stacks for cryogenic MOS devices by analyzing the oxide trap density, transconductance, Hall mobility, and critical density. The results provide valuable insights into the material physics at cryogenic temperatures.
Based on MOSFETs with four different gate stacks, we extract the oxide trap density and transconductance from the low frequency noise and DC transfer characteristics at room temperature, respectively. With the same gate stacks, Hall mobility as a function of carrier density is and the critical density is extracted at low temperatures. These physical quantities are analyzed and correlated explicitly, offering a method to qualitatively compare the quality of the four gate stacks for cryogenic MOS devices, and providing further insight into the material physics at cryogenic temperatures.

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