Circuit-Level Memory Technologies and Applications based on 2D Materials

Memory technologies and applications implemented fully or partially using emerging 2D materials have attracted increasing interest in the research community in recent years. Their unique characteristics provide new possibilities for highly integrated circuits with superior performances and low power consumption, as well as special functionalities. Here, an overview of progress in 2D-material-based memory technologies and applications on the circuit level is presented. In the material growth and fabrication aspects, the advantages and disadvantages of various methods for producing large-scale 2D memory devices are discussed. Reports on 2D-material-based integrated memory circuits, from conventional dynamic random-access memory, static random-access memory, and flash memory arrays, to emerging memristive crossbar structures, all the way to 3D monolithic stacking architecture, are systematically reviewed. Comparisons between experimental implementations and theoretical estimations for different integration architectures are given in terms of the critical parameters in 2D memory devices. Attempts to use 2D memory arrays for in-memory computing applications, mostly on logic-in-memory and neuromorphic computing, are summarized here. Finally, challenges that impede the large-scale applications of 2D-material-based memory are reviewed, and perspectives on possible approaches toward a more reliable system-level fabrication are also given, hopefully shedding some light on future research.

Automated summary

Memory technologies and applications using emerging 2D materials have gained increasing attention in recent years. This article provides an overview of progress in 2D-material-based memory technologies and applications at the circuit level. It discusses the growth and fabrication methods, reviews integrated memory circuits, compares experimental implementations with theoretical estimations, summarizes in-memory computing applications, and identifies challenges and possible approaches for more reliable system-level fabrication.