4.8 Article

Engineering Top Gate Stack for Wafer-Scale Integrated Circuit Fabrication Based on Two-Dimensional Semiconductors

期刊

ACS APPLIED MATERIALS & INTERFACES
卷 14, 期 9, 页码 11610-11618

出版社

AMER CHEMICAL SOC
DOI: 10.1021/acsami.1c22990

关键词

two-dimensional material; Al interlayer; top gate; dipole effect; logic circuit

资金

  1. National Key Research and Development Program [2021YFA1200500]
  2. Innovation Program of Shanghai Municipal Education Commission [2021-01-07-00-07-E00077]
  3. Shanghai Municipal Science and Technology Commission [21DZ1100900]
  4. National Natural Science Foundation of China [61925402]

向作者/读者索取更多资源

In this study, a non-destructive doping strategy is proposed to precisely modulate the threshold voltage of large-scale 2D semiconductors, and it is used for designing functional circuits. The strategy is also employed to optimize circuits and fabricate digital logic blocks with desired logic functions.
Y YIn recent years, two-dimensional (2D) semiconductors have attracted considerable attention from both academic and industrial communities. Recent research has begun transforming from constructing basic field-effect transistors (FETs) into designing functional circuits. However, device processing remains a bottleneck in circuit-level integration. In this work, a non-destructive doping strategy is proposed to modulate precisely the threshold voltage (V-TH) of MoS2-FETs in a wafer scale. By inserting an Al interlayer with a varied thickness between the high-k dielectric and the Au top gate (TG), the doping could be controlled. The full oxidation of the Al interlayer generates a surplus of oxygen vacancy (Vo) in the high-k dielectric layer, which further leads to stable electron doping. The proposed strategy is then used to optimize an inverter circuit by matching the electrical properties of the load and driver transistors. Furthermore, the doping strategy is used to fabricate digital logic blocks with desired logic functions, which indicates its potential to fabricate fully integrated multistage logic circuits based on wafer-scale 2D semiconductors.

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