4.6 Article

Study of Thermal Stress Fluctuations at the Die-Attach Solder Interface Using the Finite Element Method

期刊

ELECTRONICS
卷 11, 期 1, 页码 -

出版社

MDPI
DOI: 10.3390/electronics11010062

关键词

finite element method; lead-free solder; thermal stress; die-attach; thermal cycling

资金

  1. Guangdong Major Project of Basic and Applied Basic Research [2019B030302011]
  2. National Key Research and Development Program of China [2016YFB0700201]

向作者/读者索取更多资源

This study investigates the influence of different materials in a die-attach structure on the stress at the chip-solder interface. The results show that the CTE mismatch between the solder and other materials not only affects the maximum stress at the chip-solder interface, but also causes stress recovery peaks.
Solder joints in electronic packages are frequently exposed to thermal cycling in both real-life applications and accelerated thermal cycling tests. Cyclic temperature leads the solder joints to be subjected to cyclic mechanical loading and often accelerates the cracking failure of the solder joints. The cause of stress generated in thermal cycling is usually attributed to the coefficients of thermal expansion (CTE) mismatch of the assembly materials. In a die-attach structure consisting of multiple layers of materials, the effect of their CTE mismatch on the thermal stress at a critical location can be very complex. In this study, we investigated the influence of different materials in a die-attach structure on the stress at the chip-solder interface with the finite element method. The die-attach structure included a SiC chip, a SAC solder layer and a DBC substrate. Three models covering different modeling scopes (i.e., model I, chip-solder layer; model II, chip-solder layer and copper layer; and model III, chip-solder layer and DBC substrate) were developed. The 25-150 degrees C cyclic temperature loading was applied to the die-attach structure, and the change of stress at the chip-solder interface was calculated. The results of model I showed that the chip-solder CTE mismatch, as the only stress source, led to a periodic and monotonic stress change in the temperature cycling. Compared to the stress curve of model I, an extra stress recovery peak appeared in both model II and model III during the ramp-up of temperature. It was demonstrated that the CTE mismatch between the solder and copper layer (or DBC substrate) not only affected the maximum stress at the chip-solder interface, but also caused the stress recovery peak. Thus, the combined effect of assembly materials in the die-attach structure should be considered when exploring the joint thermal stresses.

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