A 2.5-GS/s Four-Way-Interleaved Ringamp-Based Pipelined-SAR ADC with Digital Background Calibration in 28-nm CMOS

A 2.5-GS/s 12-bit four-way time-interleaved pipelined-SAR ADC is presented in 28-nm CMOS. A bias-enhanced ring amplifier is utilized as the residue amplifier to achieve high bandwidth and excellent power efficiency compared with a traditional operational amplifier. A high linearity front-end is proposed to alleviate the non-linearity of the diode for ESD protection in the input PAD. The embedded input buffer can suppress the kickback noise at high input frequencies. A blind background calibration based on digital-mixing is used to correct the mismatches between channels. Additionally, an optional neural network calibration is also provided. The prototype ADC achieves a low-frequency SNDR/SFDR of 51.0/68.0 dB, translating a competitive FoM(w) of 0.48 pJ/conv.-step at 250 MHz input running at 2.5 GS/s.

Automated summary

This paper presents a 2.5-GS/s 12-bit four-way time-interleaved pipelined-SAR ADC in 28-nm CMOS, utilizing a bias-enhanced ring amplifier, high linearity front-end design, and calibration techniques to achieve competitive performance at 250 MHz input frequency. The prototype ADC achieves a low-frequency SNDR/SFDR of 51.0/68.0 dB, with a FoM(w) of 0.48 pJ/conv.-step.