相关参考文献
注意:仅列出部分参考文献,下载原文获取全部文献信息。A Scan Obfuscation Guided Design-for-Security Approach for Sequential Circuits
Rajit Karmakar et al.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS (2020)
Preventing Scan Attacks on Secure Circuits Through Scan Chain Encryption
Mathieu Da Silva et al.
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS (2019)
Stripped Functionality Logic Locking With Hamming Distance-Based Restore Unit (SFLL-hd) - Unlocked
Fangfei Yang et al.
IEEE TRANSACTIONS ON INFORMATION FORENSICS AND SECURITY (2019)
Functional Analysis Attacks on Logic Locking
Deepak Sirone et al.
2019 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE) (2019)
ScanSAT: Unlocking Obfuscated Scan Chains
Lilas Alrahis et al.
24TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC 2019) (2019)
Scan Chain Based Attacks and Countermeasures: A Survey
Xiaowei Li et al.
IEEE ACCESS (2019)
Secure Scan and Test Using Obfuscation Throughout Supply Chain
Xiaoxiao Wang et al.
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS (2018)
Robust Design-for-Security Architecture for Enabling Trust in IC Manufacturing and Test
Ujjwal Guin et al.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS (2018)
Static and Dynamic Obfuscations of Scan Data Against Scan-Based Side-Channel Attacks
Aijiao Cui et al.
IEEE TRANSACTIONS ON INFORMATION FORENSICS AND SECURITY (2017)
Provably-Secure Logic Locking: From Theory To Practice
Muhammad Yasin et al.
CCS'17: PROCEEDINGS OF THE 2017 ACM SIGSAC CONFERENCE ON COMPUTER AND COMMUNICATIONS SECURITY (2017)
On Improving the Security of Logic Locking
Muhammad Yasin et al.
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS (2016)
Fault Analysis-Based Logic Encryption
Jeyavijayan Rajendran et al.
IEEE TRANSACTIONS ON COMPUTERS (2015)
Thwarting Scan-Based Attacks on Secure-ICs With On-Chip Comparison
Jean Da Rolt et al.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS (2014)
A Primer on Hardware Security: Models, Methods, and Metrics
Masoud Rostami et al.
PROCEEDINGS OF THE IEEE (2014)
A Novel Differential Scan Attack on Advanced DFT Structures
Jean Da Rolt et al.
ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS (2013)
A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores
Geng-Ming Chiu et al.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS (2012)
SSTKR: Secure and Testable Scan Design Through Test Key Randomization
Mohammed Abdul Razzaq et al.
2011 20TH ASIAN TEST SYMPOSIUM (ATS) (2011)
ENDING PIRACY OF INTEGRATED CIRCUITS
Jarrod A. Roy et al.
COMPUTER (2010)
HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection
Rajat Subhra Chakraborty et al.
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS (2009)
Secured flipped scan-chain model for crypto-architecture
Gaurav Sengar et al.
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS (2007)
Securing designs against scan-based side-channel attacks
Jeremy Lee et al.
IEEE TRANSACTIONS ON DEPENDABLE AND SECURE COMPUTING (2007)
Secure scan: A design-for-test architecture for crypto chips
Bo Yang et al.
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS (2006)