A minimal resource high-speed routing lookup mechanism for servers with NetFPGAs

This paper studies how high-performance computer servers, equipped with Field-Programmable Gate Arrays (FPGAs), can perform high-speed routing. In particular, routing table lookup is considered since it is a key packet processing bottleneck for future routers that need to operate at Petabits-per-second. The paper defines and evaluates three routing lookup schemes used by routers/switches, using Xilinx NetFPGA SUME programmable data plane hardware boards. Two existing schemes, namely IP address-based Longest Prefix Matching and Multi-Protocol Label Switching tag-based exact matching are implemented. In addition, the paper presents a new routing scheme called No Lookup Forwarding Scheme (NLFS) that does not use conventional lookup tables. The NLFS approach adds a custom routing tag that does not require any form of (forwarding) table lookup, and independent of the Binary/Ternary Content Associate Memory (CAM) capacity in the switch/router. The experimental results show that the NLFS scheme utilizes less FPGA resources, while reducing packet lookup latency by up to 18% against longest prefix match which is the de facto lookup mechanism used in switches. The key contribution of this work is that it enables the use of NetFPGAs to reduce CAM capacity requirements in switches/routers to help reduce memory costs. The proposed scheme has several use cases, including provision of on-demand increase of packet routing capacity in data center networks and support for Network Function Virtualization-based systems.

Automated summary

This paper studies how high-performance computer servers equipped with FPGAs can perform high-speed routing. It introduces a new routing scheme called NLFS that reduces FPGA resources and packet lookup latency. The proposed scheme has potential applications in reducing switch/router costs, increasing capacity in data center networks, and supporting Network Function Virtualization-based systems.