期刊
SENSORS
卷 21, 期 22, 页码 -出版社
MDPI
DOI: 10.3390/s21227759
关键词
HPC; interconnects; communication; FPGA; data acquisition
资金
- European Unions Horizon 2020 (H2020) research and innovation program under the FET-HPC [801137]
- Ministero dellUniversita e della Ricerca (MUR) under the SPHERE PRIN2017 grant
Efficient data movement in multi-node systems is crucial for demanding data acquisition applications, with this research evaluating the use of high-bandwidth interconnect standards and remote direct memory access functions in a prototype aiming to optimize FPGA accelerator memory utilization while supporting state-of-the-art interconnect technologies.
Efficient data movement in multi-node systems is a crucial issue at the crossroads of scientific computing, big data, and high-performance computing, impacting demanding data acquisition applications from high-energy physics to astronomy, where dedicated accelerators such as FPGA devices play a key role coupled with high-performance interconnect technologies. Building on the outcome of the RECIPE Horizon 2020 research project, this work evaluates the use of high-bandwidth interconnect standards, namely InfiniBand EDR and HDR, along with remote direct memory access functions for direct exposure of FPGA accelerator memory across a multi-node system. The prototype we present aims at avoiding dedicated network interfaces built in the FPGA accelerator itself, leaving most of the resources for user acceleration and supporting state-of-the-art interconnect technologies. We present the detail of the proposed system and a quantitative evaluation in terms of end-to-end bandwidth as concretely measured with a real-world FPGA-based multi-node HPC workload.
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