期刊
NANOTECHNOLOGY
卷 33, 期 12, 页码 -出版社
IOP Publishing Ltd
DOI: 10.1088/1361-6528/ac4063
关键词
two-dimensional material; van der Waals heterostructure; ferroelectric; field effect transistor; graphene
资金
- NSFC [61674045, 21673058, 21822502]
- Key Research Program of Frontier Sciences of CAS [QYZDB-SSW-SYS031]
- Strategic Priority Research Program of CAS [XDB30000000]
- ministry of science and technology, Taiwan [MOST 107-2112-M-011-001-MY3]
- National Research Foundation Singapore [NRF-CRP22-2019-0007]
- A*STAR under its AME IRG Grant [19283074]
- AcRF Tier 2 [MOE2016-T2-1-131]
- AcRF Tier 1 [RG4/17, RG7/18]
As the size of metal oxide semiconductor field-effect transistors (FETs) is scaled down, power dissipation becomes a major challenge. The use of negative capacitance (NC) effect enables a new path to achieve a low sub-threshold swing (SS) below the Boltzmann limit. In this work, a NC-FET from an all two-dimensional (2D) metal ferroelectric semiconductor (MFS) vertical heterostructure has been demonstrated, showing steep slopes switching over a wide range of source-drain current.
As scaling down the size of metal oxide semiconductor field-effect transistors (FETs), power dissipation has become a major challenge. Lowering down the sub-threshold swing (SS) is known as an effective technique to decrease the operating voltage of FETs and hence lower down the power consumption. However, the Boltzmann distribution of electrons (so-called 'Boltzmann tyranny') implements a physical limit to the SS value. Use of negative capacitance (NC) effect has enabled a new path to achieve a low SS below the Boltzmann limit (60 mV dec(-1) at room temperature). In this work, we have demonstrated a NC-FET from an all two-dimensional (2D) metal ferroelectric semiconductor (MFS) vertical heterostructure: Graphene/CuInP2S6/MoS2. The negative capacitance from the ferroelectric CuInP2S6 has enabled the breaking of the 'Boltzmann tyranny'. The heterostructure based device has shown steep slopes switching below 60 mV dec(-1) (lowest to < 10 mV dec(-1)) over 3 orders of source-drain current, which provides an avenue for all 2D material based steep slope FETs.
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