期刊
MRS BULLETIN
卷 46, 期 10, 页码 959-966出版社
SPRINGER HEIDELBERG
DOI: 10.1557/s43577-021-00192-3
关键词
Microelectronics; Cu; Electronic structure; 2D materials; Topological
资金
- IMPACT, a center in nCORE, a Semiconductor Research Corporation (SRC) program
- NEWLIMITS, a center in nCORE, a SRC program - National Institute of Standards and Technology (NIST) [70nANB17H041]
As interconnect wires shrink in size, their electrical resistance increases, leading to signal delay and higher energy consumption. Research into new materials systems and processing methods is needed to address this size effect and produce narrow high-conductivity lines.
The electrical resistance of interconnect wires increases with decreasing size, causing signal delay and energy consumption that limits further downscaling of integrated circuits. Electron scattering at surfaces and grain-boundaries of current-technology Cu and Co conductors causes the resistivity of narrow lines to be an order of magnitude above bulk values. New materials systems and processing methods are required that mitigate this resistivity size effect and yield narrow high-conductivity lines. Promising research directions include (1) new materials with a small electron mean free path such that electron scattering at surfaces and grain-boundaries becomes negligible, (2) two-dimensional materials as new liner/barrier layers that maximize the conductor cross-sectional area and facilitate specular surface scattering, and (3) topological metals which exhibit an increasing conductivity with decreasing line width due to protected surface states that suppress electron scattering. Graphic abstract
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