A study of gate recess-width control of InP-based HEMTs by a Si3N4 passivation layer

Recess process for opening a narrow trench in the capping layer for T-shaped gates is one of the most important steps in the fabrication of InP-InAlAs/InGaAs based high electron mobility transistors, since the recessed-width strongly influences the DC/RF performances of the devices. Conventional chemical wet etch fails to well control the recess-width and its uniformity, leaving the seemingly small issue still rarely addressed so far. This work quantitatively analyzed the relationship between the recess-width and the DC/RF properties of the device by numerical simulations. To enhance the controllability of the recess-width, a 20-nm thick Si3N4 passivation layer pre-grown on the top of the capping layer was proposed. Careful comparisons of the recess-width as well as the device property with and without the passivation layer was carried out. Our results from both experiments and simulations indicate that it is promisingly feasible to control the recess-width to the desired scale by chemical wet etch when a dielectric layer such as Si3N4 is applied to protect the InGaAs capping layer from being over recessed, leading to enhanced device performance. With such an additional Si3N4 passivation layer, it is expected that the manufacturing yield of the InP-based high electron mobility transistors should be significantly enhanced with improved device performances.

Automated summary

This study analyzes the relationship between recess-width and device performance through numerical simulations, proposing a new Si3N4 passivation layer to enhance the controllability of the recess-width. Experimental and simulation results suggest that this passivation layer can improve device performance significantly.