Surface residual stress in amorphous SiO2 insulating layer on Si substrate near a Cu through-silicon via (TSV) investigated by nanoindentation

Thermomechanical reliability remains challenging in through-silicon via (TSV) manufacture, a key technology in three-dimensional packaging of integrated circuits. A primary issue in reliability is the residual stress created during manufacture and operation by mismatch in thermal expansion coefficients of Cu, the TSV filling material, with surrounding materials. Nanoindentation is suggested as a tool to measure the distribution of residual stress in the amorphous top layer near Cu TSVs. Formation of Cu TSV generates the tensile residual stress in the vicinity of the TSVs, and the maximum residual stress in top SiO2 insulating layer is 322 MPa. The residual stress increases as 652 MPa by post-heat treatments, and increases as 390 MPa for higer current density of TSVs electroplating.

Automated summary

The distribution of residual stress in through-silicon vias (TSVs) during manufacture can be measured using nanoindentation, with the stress increasing due to post-heat treatments and higher current density during TSV electroplating.