4.7 Article

Clock Synchronized Transmission of 51.2 GBd Optical Packets for Optically Switched Data Center Interconnects

期刊

JOURNAL OF LIGHTWAVE TECHNOLOGY
卷 40, 期 6, 页码 1735-1741

出版社

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JLT.2022.3148776

关键词

Clocks; Optical attenuators; Optical fibers; Optical transmitters; Phase noise; Optical receivers; Optical fiber networks; Clock synchronization; data centers; optical fiber communication; optical switching; phase noise

资金

  1. EPSRC [EP/R035342/1, EP/R041792/1, EP/V051377/1]
  2. Royal Society Paul Instrument [PIF/R1/180001]

向作者/读者索取更多资源

Optical switching is crucial for high-performance and high-speed data transmission in data center networks. Optical clock synchronization plays a vital role in clock and data recovery time. Future optical switching DCNs should support high-speed data transmission and overcome the impact of reference clock phase noise on system reliability.
Optical switching has attracted significant attention in recent research on data center networks (DCNs) as it is a promising viable route for the further scaling of hyper scale data centers, so that DCNs can keep pace with the rapid growth of machine-to-machine traffic. It has been shown that optical clock synchronization enables sub-nanosecond clock and data recovery time and is crucial to high performance optically switched DCN. Moreover, the interconnect data rate is expected to increase from the current 100 Gb/s per fiber to scale to 800 Gb/s and beyond, requiring high baud rate signaling at >50 GBd. Thus, future optically switched DCN should support >50 GBd data transmission with optical clock synchronization. Here, we demonstrate the clock-synchronized transmission of 128-byte optical packets at 51.2 GBd and study the impact of reference clock phase noise on system performance, focusing on the tolerance to the clock phase misalignment that affects the system scalability and reliability. By comparing the tolerable sampling clock phase offsets using different reference clocks, we show that a clock phase offset window of about 8 ps could be achieved with a <0.2ps source clock. Furthermore, we model and numerically study the de-correlation of clock phase noise. This allows the total jitter to be estimated, and thereby, the estimation of the transmission performance for future generations of high baud rate, clock synchronized DC interconnects.

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