期刊
IEICE ELECTRONICS EXPRESS
卷 13, 期 6, 页码 -出版社
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
DOI: 10.1587/elex.13.20160115
关键词
stochastic flash ADC; comparator; mismatch; CMOS; genetic algorithm
资金
- Adaptable and Seamless Technology Transfer Program through Target-driven R&D (A-STEP) of Japan Science and Technology Agency (JST)
- Japan Society for the Promotion of Science (JSPS) [23360155]
- University of Tokyo
- Synopsys, Inc
- Grants-in-Aid for Scientific Research [23360155] Funding Source: KAKEN
A new non-linearity reduction technique for stochastic flash ADC (SF-ADC) is proposed, focusing on distribution of comparator input-referred offsets. The SF-ADC test chip fabricated in a 130-nm CMOS process demonstrated the proposed technique can improve SNDR. In addition, the digital re-quantization also can improve the linearity more, where quantization level and fractional correction can be optimized using genetic algorithm.
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