High-Performance Multi-Stage CMOS OTA Design Using Differential Block as Compensation Network

This work presents an effective and straightforward frequency compensation scheme in CMOS three-stage amplifiers. Using a differential block in the compensation network, the proposed circuit shows independent and large first dominant pole regarding the DC gain path. The presented three-stage architecture is frequency-compensated just by a single Miller capacitor. Mathematical analysis is presented along with ample simulations that are performed using TSMC 0.18-mu m CMOS technology. According to the results, the proposed circuit shows DC gain equal to 118dB, GBW equal to 466MHz, PM equal to 74.3 degrees and 1.2mW as power consumption, respectively. The high values of DC gain and GBW make the proposed amplifier appropriate for more speedy operations such as high-speed modulators and data converters.

Automated summary

This work introduces an effective and direct frequency compensation scheme in CMOS three-stage amplifiers, with high DC gain and large GBW values. The circuit architecture is simple and requires only a single Miller capacitor for frequency compensation, making it suitable for high-speed modulators and data converters for faster operations.