期刊
IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS
卷 27, 期 3, 页码 682-694出版社
IEEE COMPUTER SOC
DOI: 10.1109/TPDS.2015.2409865
关键词
Topology; interconnections (subsystems); data communications; hardware; on-chip interconnection networks; parallel architectures; processor architectures; computer systems organization; interprocessor communications; general; communication/networking and information technology; computer systems organization topology; on-chip interconnection networks; interprocessor communications
资金
- Spanish Ministry of Education [FPU AP2010-4900, FPU FPU12/02254]
- Spanish Science and Technology Commission (CICYT) [TIN2010-21291-C02-02]
- HiPEAC European Network of Excellence
In the late years many different interconnection networks have been used with two main tendencies. One is characterized by the use of high-degree routers with long wires while the other uses routers of much smaller degree. The latter rely on two-dimensional mesh and torus topologies with shorter local links. This paper focuses on doubling the degree of common 2D meshes and tori while still preserving an attractive layout for VLSI design. By adding a set of diagonal links in one direction, diagonal networks are obtained. By adding a second set of links, networks of degree eight are built, named king networks. This research presents a comprehensive study of these networks which includes a topological analysis, the proposal of appropriate routing procedures and an empirical evaluation. King networks exhibit a number of attractive characteristics which translate to reduced execution times of parallel applications. For example, the execution times NPB suite are reduced up to a 30 percent. In addition, this work reveals other properties of king networks such as perfect partitioning that deserves further attention for its convenient exploitation in forthcoming high-performance parallel systems.
作者
我是这篇论文的作者
点击您的名字以认领此论文并将其添加到您的个人资料中。
推荐
暂无数据