4.6 Article

Demonstration of Geometrical Impact of Nanowire on GaAs1-xSbx Transistor Performance

期刊

IEEE TRANSACTIONS ON ELECTRON DEVICES
卷 69, 期 1, 页码 388-394

出版社

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2021.3130849

关键词

Compound semiconductor; GaAs1-xSbx; gate all around; nanowire; noise figure (NF); short channel effects (SCEs)

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This article demonstrates the impact of nanowire geometry on the performance of GaAs1-xSbx transistors. Triangular nanowires (TNW) show superior subthreshold slope, DIBL, and OFF current compared to circular or rectangular nanowires. Additionally, TNW exhibits higher noise figure than CNW (RNW) and the impact of temperature on device metrics was investigated, showing potential for high-performance applications through optimized nanowire geometry.
In this article, we demonstrate the impact of nanowire geometry of GaAs1-xSbx transistor. Circular, square, and triangular gate-all-around (GAA) geometries are taken to investigate the characteristics of the GaAs1-xSbx nanowire using a well-calibrated TCAD setup. This work analyzes: 1) the potential and field profiles; 2) the effect of channel mobility on the transfer characteristics (I-D-V-G) of all three geometries; 3) trend of the total gate capacitance (C-V); 4) impact of interface trap charges; 5) analysis of noise spectral density for each geometrical nanowire; and 6) impact of temperature (down to cryogenic range) on the performance metrics. We found that the equivalent distance from the center-to-surface of the nanowire is relatively small in triangular nanowire (TNW), resulting in a superior subthreshold slope (SS), DIBL, and OFF current. TNW shows similar to 8.9% (8.7%) and similar to 76.4% (75%) reduction in SS and DIBL with similar to 61.67 x (20.1 x) improvement in I-ON/I-OFF ratio as compared to circular (rectangular) nanowires. We have also analyzed the PSD of 1/f noise and noise figure (NF) of each geometrical nanowire and found that TNW has similar to 5.97% (similar to 10.1%) higher NF than CNW (RNW). Furthermore, we investigated the impact of temperature down to the cryogenic range over the device metrics such as threshold voltage (V-th), I-ON/I-OFF, transconductance (g(m)), and so on. Hence, a nanowire geometry can be optimized through the obtained design explorations and could be used for high-performance applications.

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