Improved MEOL and BEOL Parasitic-Aware Design Technology Co-Optimization for 3 nm Gate-All-Around Nanosheet Transistor

In this article, an improved parasitic-aware design technology co-optimization (DTCO) for gate-all-around nanosheet field effect transistor (GAA-NSFET) at 3 nm node is proposed. The presented DTCO flow owns two distinct features. First, a novel de-embedding strategy is designed to avoid the repeated calculation of gate-source/drain contact capacitance. Second, the parasitic resistance of the middle-end-of-line (MEOL) and back-end-of-line (BEOL) is accurately extracted, combing the front-end-of-line (FEOL) simulation and the calculation of MEOL/BEOL equivalent interconnect length. The power, performance, and area (PPA) of the benchmark circuit [15-stage ring oscillator (RO)] are collaboratively optimized. Considering the limitation of contacted gate pitch (CGP) and the process effects, the compromise of structure parameters is studied. GAA-NSFET architecture with 48% reduction in power consumption, 26% increase in speed, and 46% reduction in area is achieved, satisfying the scaling requirement from 5 to 3 nm node. All data here provide an optimization and design foundation for GAA-NSFET in future 3 nm technology node.

Automated summary

An improved parasitic-aware design technology co-optimization (DTCO) for gate-all-around nanosheet field effect transistor (GAA-NSFET) at 3 nm node is proposed in this article. The presented method optimizes power, performance, and area (PPA) of the benchmark circuit by considering structure parameters and process effects, achieving significant improvements in power consumption, speed, and area. This optimization and design foundation for GAA-NSFET in future 3 nm technology node will be valuable for further research and development.