Gate Bias Dependence of $V_{TH}$ Degradation in Planar and Trench SiC MOSFETs Under Repetitive Short Circuit Tests

The reliability of SiC MOSFETs under harsh operating conditions, such as short circuit (SC) stress, remains a major concern. In this article, a dedicated aging platform is developed to study the degradation of SiC planar- and trench-gate MOSFETs under repetitive SC conditions. The static characteristics of the devices are monitored in real-time during the test. Depending on the gate bias used in the experiments, a bidirectional $V_{TH}$ shift in both types of devices is observed, yet with a different degradation rate. The underlying degradation mechanisms investigated by device simulation reveal that the damaged region in the SiC planar-gate MOSFET is located near the channel area, while at the trench corner in the SiC trench-gate MOSFET. These research outcomes enable better understanding of the degradation mechanisms of different SiC MOSFET structures and possible ruggedness improvements in the future.

Automated summary

This article investigates the degradation of SiC MOSFETs under short circuit stress and develops an aging platform for experimental analysis. The study finds bidirectional VTH shift in different types of SiC MOSFETs with varying degradation rates. Device simulation reveals that the damaged region in SiC planar-gate MOSFET is near the channel area, while in SiC trench-gate MOSFET, it is at the trench corner.