期刊
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
卷 40, 期 11, 页码 2306-2319出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCAD.2020.3043731
关键词
Training; Common Information Model (computing); System-on-chip; Computer architecture; Hardware; Benchmark testing; Integrated circuit modeling; Deep learning; emerging nonvolatile memory (eNVM); hardware accelerator; in-memory computing; on-chip training
类别
资金
- NSF/SRC E2CDA program
- ASCENT, one of the SRC/DARPA JUMP centers
- [NSF-CCF-1903951]
DNN+NeuroSim is an integrated framework for benchmarking compute-in-memory (CIM) accelerators for deep neural networks. It automatically maps algorithms to hardware, evaluates chip-level metrics, and investigates the impact of analog nonvolatile memory (eNVM) device properties on on-chip training. This framework provides insights into synaptic devices for on-chip training and is available for both inference and training versions on GitHub.
DNN+NeuroSim is an integrated framework to benchmark compute-in-memory (CIM) accelerators for deep neural networks, with hierarchical design options from device-level, to circuit level and up to algorithm level. A python wrapper is developed to interface NeuroSim with a popular machine learning platform: Pytorch, to support flexible network structures. The framework provides automatic algorithm-to-hardware mapping, and evaluates chip-level area, energy efficiency and throughput for training or inference, as well as training/inference accuracy with hardware constraints. Our prior inference version of DNN+NeuroSim framework available at https://github.com/neurosim/DNN_NeuroSim_V1.2 was developed to estimate the impact of reliability in synaptic devices, and analog-to-digital converter (ADC) quantization loss on the accuracy and hardware performance of an inference engine. In this work, we further investigated the impact of the analog emerging nonvolatile memory (eNVM)'s nonideal device properties for on-chip training. By introducing the nonlinearity, asymmetry, device-to-device and cycle-to-cycle variation of weight update into the python wrapper, and peripheral circuits for error/weight gradient computation in NeuroSim core, we benchmarked CIM accelerators based on state-of-the-art SRAM and eNVM devices for VGG-8 on CIFAR-10 dataset, revealing the crucial specs of synaptic devices for on-chip training. The latest training version of the DNN+NeuroSim framework is available at https://github.com/neurosim/DNN_NeuroSim_V2.1.
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