期刊
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
卷 69, 期 1, 页码 25-29出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCSII.2021.3083545
关键词
Delay-locked loop; low phase error; phase detector; duty-cycle corrector; voltage-controlled delay
资金
- National Natural Science Foundation of China [61674122]
This paper presents a four-phase delay-locked loop (DLL) with low phase error, low power consumption, and small area for time-to-digital conversion application. A highly matched single-ended differential single-ended voltage-controlled delay line is proposed to improve the phase uniformity of the multiple output signals. Additionally, a digital auxiliary duty-cycle corrector is designed to adjust the width of the output signal and reduce the pulse width error.
In this brief, a four-phase delay-locked loop (DLL) with low phase error, low power consumption, and small area is presented for time-to-digital conversion application. A highly matched single-ended differential single-ended voltage-controlled delay line is proposed to improve the phase uniformity of these multiple output signals. A digital auxiliary duty-cycle corrector is designed to adjust the width of the output signal to reduce the pulse width error and to make the duty cycle of each output signal approximately 50%. Designed using 0.18-mu m CMOS technology, this DLL occupies an active area of 111.32 mu m x 82.74 mu m. With a 1.8 V supply voltage and a 250 MHz operating frequency, the measured power consumption and output phase error rate of this DLL are 2.28 mW and 1.3%, respectively.
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