期刊
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
卷 69, 期 4, 页码 1595-1605出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCSI.2021.3139736
关键词
FeFETs; Microprocessors; Transistors; Logic gates; Writing; Switches; Voltage measurement; Ferroelectric field effect transistor (FeFET); memory; emerging memory technology; array architecture
资金
- European Research Council through the European Union [757259]
- United States-Israel Binational Science Foundation (NSF-BSF) [2015709]
- European Fund for Regional Development (EFRD), Europe
- Saxon Parliament
- European Research Council (ERC) [757259] Funding Source: European Research Council (ERC)
This paper proposes a memory architecture called crossed-AND (C-AND) for FeFET memory, which addresses the asymmetric switching voltage issue and enables fast read and write operations for entire words. It also reduces read errors and write disturbs.
Ferroelectric field effect transistor (FeFET) memory has shown the potential to meet the requirements of the growing need for fast, dense, low-power, and non-volatile memories. In this paper, we propose a memory architecture named crossed-AND (C-AND), in which each storage cell consists of a single ferroelectric transistor. The write operation is performed using different write schemes and different absolute voltages, to account for the asymmetric switching voltages of the FeFET. It enables writing an entire wordline in two consecutive cycles and prevents current and power through the channel of the transistor. During the read operation, the current and power are mostly sensed at a single selected device in each column. The read scheme additionally enables reading an entire word without read errors, even along long bitlines. Our Simulations demonstrate that, in comparison to the previously proposed AND architecture, the C-AND architecture diminishes read errors, reduces write disturbs, enables the usage of longer bitlines, and saves up to 2.92X in memory cell area.
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