期刊
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
卷 69, 期 1, 页码 88-99出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCSI.2021.3096242
关键词
Switches; Capacitors; Capacitance; Linearity; Sigma-delta modulation; Calibration; Registers; Analog-to-digital converter (ADC); capacitor swapping; digital-to-analog converter (DAC); successive approximation register (SAR); binary-window DAC switching
资金
- Ministry of Science and Technology of Taiwan [MOST 109-2221-E-011-139]
This paper presents a 16-bit ADC with excellent SFDR, utilizing special DAC switching schemes and capacitor swapping scheme to enhance performance. The measured results demonstrate that the ADC performs well in various metrics, with small size and low power consumption.
This paper presents a 16-bit successive approximation register analog-to-digital converter (ADC) achieving over-100 dB spurious-free dynamic range (SFDR). This ADC uses V $_{{CM}}$ -based and binary-window digital-to-analog converter (DAC) switching schemes to improve the signal-to-noise and distortion ratio (SNDR). Moreover, a level-2 capacitor swapping scheme is proposed to achieve superior DAC linearity by using two intrinsic true random number sequences. A prototype ADC is fabricated in 180 nm CMOS technology and occupies an active area of 0.53 mm(2). At 1 MS/s, it consumes a total power of 1.05 mW from a supply of 1.8 V. The measured differential and integral nonlinearity are -0.65/+0.45 and -2.2/+2.1 least significant bit. With an input of 1 kHz, the measured SNDR and SFDR are 83 dB and 100 dB. The effective number of bits is 13.5, which is equivalent to a Schreier figure-of-merit of 169.8 dB.
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