4.6 Article

An Ultra-Low-Power Fully-Static Contention-Free Flip-Flop With Complete Redundant Clock Transition and Transistor Elimination

期刊

IEEE JOURNAL OF SOLID-STATE CIRCUITS
卷 56, 期 10, 页码 3039-3048

出版社

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2021.3077074

关键词

Clocks; Transistors; Reliability; Integrated circuit reliability; Redundancy; Power demand; Semiconductor device measurement; Effective clock load; flip-flop (FF); redundant clock; redundant transistor; reliability

资金

  1. Basic Science Research and Basic Research Laboratory Program through the National Research Foundation of Korea (NRF) - Ministry of Science and ICT [2019R1A2C4070438, 2020R1A4A2002806]
  2. National Research Foundation of Korea [2019R1A2C4070438] Funding Source: Korea Institute of Science & Technology Information (KISTI), National Science & Technology Information Service (NTIS)

向作者/读者索取更多资源

The REFF flip-flop eliminates redundancies to achieve low-power and reliable operation, working reliably down to 0.31 V. Tests have shown significant power reduction compared to conventional flip-flops, with the REFF remaining functional at as low as 0.28 V.
A redundancy eliminated flip-flop (REFF) is proposed targeting wide-range voltage scalability (1-0.3 V). Two types of redundancies are eliminated in the REFF to achieve low-power (LP) and reliable operation even in the sub-threshold voltage regime. First, redundant internal clock transitions are eliminated without degrading reliability by finding the optimal way of generating internally inverted clock to reduce dynamic power consumption. Then redundant transistors are identified and eliminated with a topological and logical method while keeping it fully static and contention-free. The simulation results show that the REFF is currently the only FF that fully eliminates redundancy while maintaining static and contention-free operation, and is reliable down to 0.31 V in Monte-Carlo simulations. The measurement results from a test chip fabricated in 28-nm LP CMOS technology show that the measured power is reduced by 69.7%/58.7% with 0%/10% activity at 1 V and by 70.3%/58.2% with 0%/10% activity at 0.4 V compared to the conventional transmission gate flip-flop (TGFF). A total of 100 dies from five corners were tested to demonstrate the reliability, and the REFF was functional down to 0.28 V.

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