Performance Evaluation of Scaled ZnO Stacked Nanosheet Channel Ternary Field Effect Transistor

Ternary logic device technologies have been actively researched due to the potential benefits such as lower power consumption, smaller device count, smaller area, and higher data processing density, compared to their binary counterparts. In this work, scaling prospect of ZnO stacked nanosheet channel ternary field effect transistor has been investigated. The benefits of scaling geometric parameters such as gate dielectric thickness, channel length, and source/drain charge injection area are examined. 90 % lower power consumption in the intermediate state is achieved at V-dd = 1 V with a noise margin of 130 mV, compared to other emerging ternary logic devices. The feasibility for stable ternary circuit operation is confirmed as well.

Automated summary

This work investigates the scaling prospect of ZnO stacked nanosheet channel ternary field effect transistor, as well as the impact of scaling geometric parameters on its performance. The results show that compared to other ternary logic devices, this device has lower power consumption and higher noise margin in the intermediate state. The feasibility for stable ternary circuit operation is also confirmed.