期刊
IEEE ELECTRON DEVICE LETTERS
卷 42, 期 11, 页码 1623-1626出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2021.3113024
关键词
Stress; Logic gates; Degradation; Thin film transistors; Transient analysis; Electrodes; Annealing; A-IGZO; thin-film transistor; gate bias stress; drain bias stress
资金
- National Natural Science Foundation of China [61974101, 61971299]
- Suzhou Science and Technology Bureau [SYG201933]
- Natural Science Foundation of Jiangsu Province of China [SBK20201201]
- State Key Laboratory of ASIC and System, Fudan University [2021KF005]
- Jiangsu Higher Education Institute of China [19KJB510058]
The study demonstrates that annealing at 400 degrees C in O-2 atmosphere can effectively reduce trap states in the a-IGZO channel, improving the stability of TFTs.
Amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) severely degrade under AC gate bias stress and AC drain bias stress, whose transfer curves respectively undergo positive shifts of 6.3 and 14.2 V after a stress time of 3000 s with a stress amplitude of 20 V. In this study, annealing at 400 degrees C in O-2 atmosphere is performed to effectively reduce the acceptor-like trap states in the a-IGZO channel and the electric field in the etching-stop layer under the extended drain electrode, which participate in dynamic and DC degradation mechanisms, respectively. Thus, a-IGZO TFTs exhibiting excellent stability without any shift of the transfer curve under the same AC gate bias stress and AC drain bias stress are experimentally demonstrated simultaneously.
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