SiO2 Fin-Based Flash Synaptic Cells in AND Array Architecture for Binary Neural Networks

An oxide fin-based AND flash memory synaptic device is proposed and fabricated using a spacer patterning technology for a hardware-based binary neural network (BNN). A fin-like curved channel structure provides local electric field enhancement, which improves programming efficiency compared to planar-type flash synaptic devices. The fin-based AND flash cell exhibits a high on/off current ratio (>10(5)) with sub-pA off current, and a low programming voltage (< 9 V) is used to achieve a sufficient dynamic range of synaptic weights (>10(3)) for BNNs. Furthermore, a hardware-based BNN using novel two cell-based synaptic devices arranged in AND array architecture is proposed to implement parallel XNOR operation and bit-counting. Proposed BNN using the synapse model with measured dynamic range and retention property shows only < 0.5 % degradation of classification accuracy compared to the baseline accuracy, which is suitable to perform off-chip event-driven computation using parallel read-out operations.

Automated summary

An oxide fin-based AND flash memory synaptic device is proposed and fabricated for a hardware-based binary neural network. The device features a fin-like curved channel structure, providing local electric field enhancement for improved programming efficiency. The fin-based AND flash cell exhibits high on/off current ratio, low off current, and low programming voltage, resulting in a sufficient dynamic range of synaptic weights for BNNs. Additionally, a hardware-based BNN using a novel two-cell synaptic device arrangement is proposed, enabling parallel XNOR operation and bit-counting. Experimental results show only slight degradation in classification accuracy compared to the baseline accuracy, making it suitable for off-chip event-driven computation.