期刊
IEEE TRANSACTIONS ON ELECTRON DEVICES
卷 63, 期 12, 页码 5004-5011出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TED.2016.2616483
关键词
Brain-inspired hardware; cognitive computing; neuromorphic computing; phase change memory(PCM); resistive memory
资金
- SONIC, one of six centers of STARnet, a Semiconductor Research Corporation Program - MARCO
- DARPA
- NSF Expedition on Computing under Visual Cortex on Silicon [1317470]
- Member Companies of the Stanford Non-Volatile Memory Technology Research Initiative
- Stanford SystemX Alliance
- Division of Computing and Communication Foundations
- Direct For Computer & Info Scie & Enginr [1317407] Funding Source: National Science Foundation
- Division of Computing and Communication Foundations
- Direct For Computer & Info Scie & Enginr [1317470] Funding Source: National Science Foundation
Current large-scale implementations of deep learning and data mining require thousands of processors, massive amounts of off-chip memory, and consume giga-joules of energy. New memory technologies, such as nanoscale two-terminal resistive switching memory devices, offer a compact, scalable, and low-power alternative that permits on-chip colocated processing and memory in fine-grain distributed parallel architecture. Here, we report the first use of resistive memory devices for implementing and training a restricted Boltzmann machine (RBM), a generative probabilistic graphical model as a key component for unsupervised learning in deep networks. We experimentally demonstrate a 45-synapse RBM realized with 90 resistive phase change memory (PCM) elements trained with a bioinspired variant of the contrastive divergence algorithm, implementing Hebbian and anti-Hebbian weight updates. The resistive PCM devices show a twofold to tenfold reduction in error rate in a missing pixel pattern completion task trained over 30 epochs, compared with untrained case. Measured programming energy consumption is 6.1 nJ per epoch with the PCM devices, a factor of similar to 150 times lower than the conventional processor-memory systems. We analyze and discuss the dependence of learning performance on cycle-to-cycle variations and number of gradual levels in the PCM analog memory devices.
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