Area-Efficient Bevel-Edge Termination Techniques for SiC High-Voltage Devices

This paper reviews the bevel-edge termination techniques for silicon carbide (SiC) power devices, such as bevel junction termination extension (JTE), resistive-bevel termination, bevel-assisted JTE, and positive-bevel termination. The proposed bevel-edge termination techniques significantly reduce the chip size for SiC power devices. PiN diodes and test structures were fabricated to quantify the relative performance of the proposed structures. Quantitative comparison in chip size reduction, process schemes, and future research directions is discussed in detail.