Fast-switching SOI-LIGBT with compound dielectric buried layer and assistant-depletion trench

A lateral insulated gate bipolar transistor (LIGBT) based on silicon-on-insulator (SOI) structure is proposed and investigated. This device features a compound dielectric buried layer (CDBL) and an assistant-depletion trench (ADT). The CDBL is employed to introduce two high electric field peaks that optimize the electric field distributions and that, under the same breakdown voltage (BV) condition, allow the CDBL to acquire a drift region of shorter length and a smaller number of stored carriers. Reducing their numbers helps in fast-switching. Furthermore, the ADT contributes to the rapid extraction of the stored carriers from the drift region as well as the formation of an additional heat-flow channel. The simulation results show that the BV of the proposed LIGBT is increased by 113% compared with the conventional SOI LIGBT of the same length L (D). Contrastingly, the length of the drift region of the proposed device (11.2 mu m) is about one third that of a traditional device (33 mu m) with the same BV of 141 V. Therefore, the turn-off loss (E (OFF)) of the CDBL SOI LIGBT is decreased by 88.7% compared with a conventional SOI LIGBT when the forward voltage drop (V (F)) is 1.64 V. Moreover, the short-circuit failure time of the proposed device is 45% longer than that of the conventional SOI LIGBT. Therefor, the proposed CDBL SOI LIGBT exhibits a better V (F)-E (OFF) tradeoff and an improved short-circuit robustness.

Automated summary

A lateral insulated gate bipolar transistor based on silicon-on-insulator structure is proposed and investigated, which features a compound dielectric buried layer and an assistant-depletion trench. The simulation results show that the proposed device has a higher breakdown voltage, a shorter drift region, a lower turn-off loss, and better short-circuit robustness compared to the conventional SOI transistor.