Impact of gate offset in gate recess on DC and RF performance of InAlAs/InGaAs InP-based HEMTs

A set of 100-nm gate-length InP-based high electron mobility transistors (HEMTs) were designed and fabricated with different gate offsets in gate recess. A novel technology was proposed for independent definition of gate recess and T-shaped gate by electron beam lithography. DC and RF measurement was conducted. With the gate offset varying from drain side to source side, the maximum drain current (I (ds,max)) and transconductance (g (m,max)) increased. In the meantime, f (T) decreased while f (max) increased, and the highest f (max) of 1096 GHz was obtained. It can be explained by the increase of gate-source capacitance and the decrease of gate-drain capacitance and source resistance. Output conductance was also suppressed by gate offset toward source side. This provides simple and flexible device parameter selection for HEMTs of different usages.

Automated summary

A set of 100-nm gate-length InP-based HEMTs were designed and fabricated with different gate offsets using electron beam lithography. DC and RF measurements were conducted, and the results showed that the gate offset variation led to an increase in maximum drain current and transconductance, a decrease in f(T), and an increase in f(max). Furthermore, gate offset towards the source side suppressed the output conductance.