期刊
IEEE JOURNAL OF SOLID-STATE CIRCUITS
卷 51, 期 1, 页码 18-30出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2015.2457920
关键词
Digital LDO; DLDO; DVFS; energy efficiency; fully integrated; graphics execution core; IVR; SCVR; switched capacitor voltage regulator
资金
- U.S. Government (DARPA)
A digitally-controlled fully integrated voltage regulator (IVR) enables wide autonomous DVFS in a 22 nm graphics execution core. Part of the original power header is converted into a hybrid power stage to support digital low-dropout (DLDO), and switched-capacitor voltage regulator (SCVR) modes, in addition to the original bypass and sleep modes. Using voltage sensing, tunable replica circuit, or a core warning signal, the IVR detects and quickly responds to fast voltage droops to support fast dynamic workload changes without performance degradation. In a prototype, a 3D graphics execution core is powered up by the proposed hybrid IVR demonstrating measured 26% and 82% reduction in core energy in the turbo and the near-threshold voltage (NTV) modes, respectively. The total area overhead of the proposed hybrid IVR is 4% of the core compared to 2% from the original power header. Our digitally assisted control for the droop response shows similar to 75% core frequency improvement at 0.84 V.
作者
我是这篇论文的作者
点击您的名字以认领此论文并将其添加到您的个人资料中。
推荐
暂无数据