A 0.076 mm2 12 b 26.5 mW 600 MS/s 4-Way Interleaved Subranging SAR-ΔΣ ADC With On-Chip Buffer in 28 nm CMOS

A 0.076 mm(2) 12b 28 nm 600 MS/s 4-way time interleaved ADC with on chip buffer is presented. The usage of a subranging scheme consisting of a coarse SAR ADC followed by an incremental Delta Sigma fine converter provides better suppression of thermal noise added during conversion for a given power compared to a conventional SAR. The ADC area has been optimized by using a segmented charge-sharing charge-redistribution DAC. The prototype achieves an SNDR of 60.7 dB and 58 dB at low and high frequency, respectively, while consuming 26 mW.