Fermi Level Pinning Dependent 2D Semiconductor Devices: Challenges and Prospects

Motivated by the high expectation for efficient electrostatic modulation of charge transport at very low voltages, atomically thin 2D materials with a range of bandgaps are investigated extensively for use in future semiconductor devices. However, researchers face formidable challenges in 2D device processing mainly originated from the out-of-plane van der Waals (vdW) structure of ultrathin 2D materials. As major challenges, untunable Schottky barrier height and the corresponding strong Fermi level pinning (FLP) at metal interfaces are observed unexpectedly with 2D vdW materials, giving rise to unmodulated semiconductor polarity, high contact resistance, and lowered device mobility. Here, FLP observed from recently developed 2D semiconductor devices is addressed differently from those observed from conventional semiconductor devices. It is understood that the observed FLP is attributed to inefficient doping into 2D materials, vdW gap present at the metal interface, and hybridized compounds formed under contacting metals. To provide readers with practical guidelines for the design of 2D devices, the impact of FLP occurring in 2D semiconductor devices is further reviewed by exploring various origins responsible for the FLP, effects of FLP on 2D device performances, and methods for improving metallic contact to 2D materials.

Automated summary

This article discusses the impact of Fermi level pinning (FLP) in 2D semiconductor devices and its causes. The authors indicate that FLP is mainly due to inefficient doping into 2D materials, vdW gap at the metal interface, and hybridized compounds formed under contacting metals. The article further explores the effects of FLP on 2D device performance and methods for improving metallic contact to 2D materials.