L2C: Combining Lossy and Lossless Compression on Memory and I/O

In this article, we introduce (LC)-C-2, a hybrid lossy/lossless compression scheme applicable both to the memory subsystem and I/O traffic of a processor chip. (LC)-C-2 employs general-purpose lossless compression and combines it with state-of-the-art lossy compression to achieve compression ratios up to 16:1 and to improve the utilization of chip's bandwidth resources. Compressing memory traffic yields lower memory access time, improving system performance, and energy efficiency. Compressing I/O traffic offers several benefits for resource-constrained systems, including more efficient storage and networking. We evaluate (LC)-C-2 as a memory compressor in simulation with a set of approximation-tolerant applications. (LC)-C-2 improves baseline execution time by an average of 50% and total system energy consumption by 16%. Compared to the lossy and lossless current state-of-the-art memory compression approaches, (LC)-C-2 improves execution time by 9% and 26%, respectively, and reduces system energy costs by 3% and 5%, respectively. I/O compression efficacy is evaluated using a set of real-life datasets. (LC)-C-2 achieves compression ratios of up to 10.4:1 for a single dataset and on average about 4:1, while introducing no more than 0.4% error.

Automated summary

This article introduces a hybrid lossy/lossless compression scheme (LC)-C-2, which is applicable to both the memory subsystem and I/O traffic of a processor chip. By combining general-purpose lossless compression with state-of-the-art lossy compression, (LC)-C-2 achieves high compression ratios and improves the utilization of chip's bandwidth resources, resulting in improved system performance and energy efficiency.