Buried 3D spot-size converters for silicon photonics

In this article, an efficient spot-size converter (SSC) for low-loss optical mode transition between large and small wave-guides based upon a buried three-dimensional (3D) taper is demonstrated. The SCC can pave the way for scalable, low-loss coupling between on-chip waveguides of different sizes and with external components such as optical fibers and III-V active components, and it can be a key element in solving the challenges surrounding the economic high volume packaging and assembly of photonic integrated circuits. Through the use of a bespoke fabrication process, continual tapering of the waveguide dimensions both in width and height is achieved, offering minimal perturbance of the optical mode throughout the structure. The SSC exploits the space of the buried oxide (BOX) on a standard silicon-on-insulator wafer, leaving a planar top wafer surface, meaning that, crucially, further processing of the wafer is not inhibited in any way. Fabricated proof-of-concept devices demonstrate coupling between standard single-mode 220 nm thick silicon waveguides and large-core waveguides with dimensions about 3 mu m wide and 1.5 mu m height with BOX thickness of 2 mu m. Coupling losses as low as 0.56 dB are achieved, limited mostly by the material loss of the polysilicon used. Substantial improvements can be yielded by simply changing the infill material and through optimization of the fabrication process and design. The demonstrated SSC approach can further be applied to other photonic platforms such as silicon nitride on insulator and so on. (C) 2021 Optical Society of America under the terms of the OSA Open Access Publishing Agreement

Automated summary

This article demonstrates an efficient spot-size converter (SSC) based on a buried three-dimensional (3D) taper for low-loss optical mode transition between large and small waveguides. The SSC can facilitate scalable, low-loss coupling between on-chip waveguides of different sizes and external components, addressing challenges in packaging and assembly of photonic integrated circuits.