Flexible high-performance organic thin film transistors and PMOS inverters: Trap controlled grain boundaries and contact resistance effect in different channel length devices

Printed high-performance organic thin film transistors (OTFTs) are fabricated on flexible polyethylene naphthalate (PEN) substrate for low-voltage operation. Gate, source and drain electrodes are inkjet-printed using conductive silver ink, while chemical vapor deposition grown parylene is used as dielectric layer. We used a blend of 2,7-dihexyl-dithieno[2,3-d;2 ',3 '-d ']benzo[1,2-b;4,5-b ']dithiophene (DTBDT-C6) and polystyrene (PS), for active p-type organic semiconducting material, and deposited by a dispenser system to achieve 0.66 cm2/Vs mobility at VGS = -6 V. For a set of 30 OTFT devices, the uniformity in device characteristics is illustrated by plotting the histograms for on current, mobility, and threshold voltage (VTh). Mobility decrease for small channel length due to greater contribution of contact resistance, while negative VTh shift occurs because of the generation of hole traps at dielectric-semiconductor interface attributed to moisture present. Electron traps on grain boundaries of the active semiconducting layer causes positive shift in VTh. By using these high mobility OTFT devices, two different low-voltage operation PMOS (P-channel metal-oxide-semiconductor) inverters are fabricated for which high signal gain value of 24.86 is achieved at VDD = -5 V.

Automated summary

This study demonstrates the fabrication of high-performance OTFT devices on flexible PEN substrate using inkjet-printed electrodes and parylene dielectric layer. The uniformity in device characteristics and mobility decrease are influenced by factors such as contact resistance, moisture, and electron traps on grain boundaries of the active semiconducting layer. The high mobility OTFT devices are utilized to fabricate low-voltage operation PMOS inverters with a high signal gain value achieved.