Nanosheet field effect transistors-A next generation device to keep Moore's law alive: An intensive study

Incessant downscaling of feature size of multi-gate devices such as FinFETs and gate-all-around (GAA) nanowire (NW)-FETs leads to unadorned effects like short channel effects (SCEs) and self-heating effects (SHEs) which lim-its their performance and causes reliability issues. FinFET technology has resulted in a remarkable performance up to a feature size of 7 nm. The research community is expecting that GAA NW-FETs will take over FinFET technology from 7 nm to 5 nm. However, further shrinking of feature size to 3 nm will impose severe challenges to the performance of these aforesaid multi-gate devices. Subsequently, the electron device designer community needs to look for alternative device designs like nanosheet FETs (NS-FETs) to overcome the limitations of the FinFET and GAA NW-FETs technologies. The driving force behind the emergence of these NS-FETs is their ability to scale down even below a feature size of 5 nm with negligible short channel effects. Therefore, in this review article we have intensively investigated the NS-FETs in terms of impact of geometrical scaling, substrate mate-rial effects, parasitic channel effects, thermal effects, compatibility with different metal gates, and source/drain (S/D) metal depth effect. Consequently, it can be concluded that vertically stacked NS-FET is the most promis-ing solution for future digital/analog integrated circuit applications due to their outstanding capability to keep Moore's Law alive.

Automated summary

The incessant downscaling of feature size in multi-gate devices poses challenges such as short channel effects and self-heating effects. To overcome these limitations, the research community is looking towards nanosheet FETs as a promising solution due to their ability to scale down while minimizing short channel effects.