期刊
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
卷 29, 期 8, 页码 1596-1600出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TVLSI.2021.3086897
关键词
Transistors; Logic gates; Transient analysis; Layout; Radiation hardening (electronics); Analytical models; Tools; Arithmetic circuit; fault tolerance; full-adder; radiation hardening; redundancy; single event transient (SET)
In this study, a new radiation-hardened-by-design full-adder cell on 45-nm technology was proposed, which reduced SET sensitivity through selective duplication of sensitive transistors and improved performance and power overhead. Experimental results showed a 62% reduction in SET sensitivity compared to the unhardened design.
Single event transients (SETs) have become increasingly problematic for modern CMOS circuits due to the continuous scaling of feature sizes and higher operating frequencies. Especially when involving safety-critical or radiation-exposed applications, the circuits must be designed using hardening techniques. In this brief, we present a new radiation-hardened-by-design full-adder cell on 45-nm technology. The proposed design is hardened against transient errors by selective duplication of sensitive transistors based on a comprehensive radiation-sensitivity analysis. Experimental results show a 62% reduction in the SET sensitivity of the proposed design with respect to the unhardened one. Moreover, the proposed hardening technique leads to improvement in performance and power overhead and zero area overhead with respect to the state-of-the-art techniques applied to the unhardened full-adder cell.
作者
我是这篇论文的作者
点击您的名字以认领此论文并将其添加到您的个人资料中。
推荐
暂无数据