期刊
IEEE TRANSACTIONS ON NUCLEAR SCIENCE
卷 68, 期 8, 页码 2286-2293出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TNS.2021.3096162
关键词
Timing; Field programmable gate arrays; Registers; Energy measurement; Data acquisition; Impedance; Current measurement; Field-programmable gate array (FPGA); linearity; low power; silicon photomultiplier (SiPM) readout; successive-approximation-register (SAR) analog-to-digital converter (ADC); time-to-digital converter (TDC); timing and energy measurement
This article presents a low-power highly linear multichannel data acquisition system for SiPM readout, which includes key technologies such as charge readout, ADC design, TDC implementation, and circuit performance evaluation.
This article presents a low-power highly linear multichannel data acquisition (DAQ) system for silicon photomultiplier (SiPM) readout. A low-input impedance current-mode front-end with a programmable current gain is developed to achieve high-precision charge readout over a large dynamic range. An integrated 10-bit successive-approximation-register (SAR) analog-to-digital converter (ADC) shared by 16 readout channels in a time-multiplexed manner is designed to reduce the overall chip area and power consumption of the SiPM readout. Implementation challenges of field-programmable gate array (FPGA)-based time-to-digital converters (TDCs) including bubble error, zero length bins, interclock region nonlinearity, and chain overflow, are addressed for high accuracy timing measurement. Multichain averaging is developed to improve the TDC linearity. Fabricated in a 180-nm CMOS process, the current-mode 16-channel readout application-specific integrated circuit (ASIC) achieves 3.6% maximum gain nonlinearity over an input dynamic range of 800 pC with dissipating 3.89 mW of power per readout channel, and the ADC achieves an SFDR of 58.34 dB and an SNDR of 51.37 dB at 16 MS/s. Implemented in a Xilinx 28-nm Kintex-7 FPGA, the 32-channel TDC achieves a 15-ps root mean square (RMS) resolution, a differential nonlinearity (DNL) of less than 4 ps, and an integral nonlinearity (INL) of less than 10 ps.
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