期刊
IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES
卷 69, 期 7, 页码 3335-3347出版社
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TMTT.2021.3074160
关键词
Input matching; low-noise amplifier (LNA); millimeter wave (mm wave); noise figure (NF); transformer; wideband
资金
- National Key Research and Development Program of China [2018YFB1802000]
- Key-Area Research and Development Program of Guangdong Province [2018B010115001]
- Guangdong Innovative and Entrepreneurial Research Team Program [2017ZT07X032]
The proposed LNA incorporates a wideband low-noise design with a novel input matching network and transformers to reduce noise figure, achieving an NF lower than 4.5 dB over a wide operating bandwidth. Furthermore, utilizing pole-tuning technique and current-reuse technique, the design achieves wider gain bandwidth and low power consumption.
A wideband low-noise amplifier (LNA) featuring transformer-based wideband input matching is proposed for millimeter-wave applications. By analyzing the properties of conventional series input matching networks, which were widely employed in narrowband LNAs and shunt-series matching networks for bandwidth extension, a novel input matching network possessing the merits of both was proposed. For further bandwidth extension, another peak of input impedance at a higher frequency is introduced for the proposed input matching network. Moreover, it is proved that the proposed input matching network can suppress the gate resistor noise, resulting in significant noise figure (NF) improvement of an LNA. On the other hand, the NF is further reduced by connecting a transformer between the two amplification stages, which helps suppress the noise contribution from the second stage, leading to an LNA design with NF lower than 4.5 dB over a very wide operating bandwidth. To enhance the gain bandwidth, the peak distribution, including both shunt peaking and series peaking, is discussed. By appropriately distributing these peaks, which is also known as the pole-tuning technique, a wider gain bandwidth can be obtained. To validate the proposed techniques, an LNA with two common-source (CS) stages is designed and fabricated using a 65-nm CMOS process, and the overall chip size, including all pads, is only 0.26 mm(2). The two CS stages are cascoded for dc biasing to reduce the power consumption. Experimental results show that a peak gain of 13.5 dB is achieved within a -3-dB bandwidth from 19.2 to 42.6 GHz. The measured NF is 3.1-4.5 dB, and the input 1-dB gain compression point (IP1 dB) ranges from -13.54 to -9.89 dBm in the entire gain bandwidth. The input return loss $S_{11}$ is less than -10 dB over a frequency range of 16.8-38.9 GHz. Moreover, benefiting from the current-reuse technique, the power consumption of the LNA is only 6.36 mW.
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